ENEL373-20S1 (C) Semester One 2020

Digital Electronics and Devices

15 points

Start Date: Monday, 17 February 2020
End Date: Sunday, 21 June 2020
Withdrawal Dates
Last Day to withdraw from this course:
  • Without financial penalty (full fee refund): Friday, 28 February 2020
  • Without academic penalty (including no fee refund): Friday, 29 May 2020


This is an in-depth course that takes logic theory and applies it to the analysis, synthesis and simulation of digital logic circuits; and the application and theory of implementing electronics devices. The course also covers the implementation of circuit designs using a hardware description language with specific application to the design of ALUs and simple microprocessors. We also cover the digital assumption made of switching analogue circuits, look at the physical implementation of transistors, circuits based on them and interconnecting components. Assumed knowledge in basic computer architecture and electronics.

Topics covered include:

1. Digital Logic: Truth tables, boolean expressions, sets; Boolean logic and manipulation; SOP and POS form; sufficiency; logic minimisation and k-maps; combinational logic; sequential design and finite state machines

2. Computer Architecture: Hardware description language design (VHDL); register specification; adder design; ALU design; basic execution unit design; integration of design units to build a simple CPU

3. CMOS Implementation of Digital Circuits: Logic thresholds; rise and fall times; noise margins; CMOS inverter; physical implementation on digital characteristics; CMOS fabrication; synthesis of logic in CMOS; effect of capacitance; gate-power prediction, RS flip-flop realisation in CMOS

4. System-on-a-chip: SoC components; interconnects; external chip interfaces; optoelectronic components; photodetectors; lasers; radio frequency devices; RF transistors and diodes; power microelectronic devices

Learning Outcomes

  • At this end of this course students will be able to:
  • Understand and apply Boolean algebra including:  de Morgan's theory, sufficiency, SOP and POS form.
  • Obtain logic equivalences and minimise logic expressions using K-maps.
  • Analyse and synthesize combinational logic circuits from logic gates.
  • Understand the operation, and be able to synthesize, sequential logic and finite state machines.
  • Describe logic hardware in VHDL for implementation and simulation.
  • Understand the architecture and operation of a CPU and be able to implement a basic CPU in VHDL.
  • Obtain the output voltage versus input voltage transfer function of a CMOS inverter.
  • Obtain noise margins of CMOS gate and understand their significance.
  • Predict the propagation delays of a CMOS inverter.
  • Directly synthesize a logic expression in CMOS including calculating gate widths of each MOSFET.
  • Predict voltage and current waveforms at either end of a transmission line driven and terminated by CMOS inverters.
  • Understand the need for power-supply de-coupling.
  • Predict power consumed by a gate for a certain clock speed and capacitive load.
  • Demonstrate knowledge of a RS flip-flop circuit in CMOS and aware that it is the basic memory unit.
  • Demonstrate knowledge of System-on-a-Chip concepts and related devices.



ENEL391 and ENCE362

Timetable 2020

Students must attend one activity from each section.

Lecture A
Activity Day Time Location Weeks
01 Monday 16:00 - 17:00 17 Feb - 29 Mar
20 Apr - 26 Apr
4 May - 31 May
Lecture B
Activity Day Time Location Weeks
01 Tuesday 13:00 - 14:00 17 Feb - 29 Mar
20 Apr - 31 May
Lecture C
Activity Day Time Location Weeks
01 Thursday 13:00 - 14:00 17 Feb - 22 Mar
20 Apr - 31 May
Lab A
Activity Day Time Location Weeks
01 Friday 09:00 - 11:00 17 Feb - 22 Mar
20 Apr - 31 May
02 Friday 11:00 - 13:00 17 Feb - 22 Mar
20 Apr - 31 May
03 Monday 09:00 - 11:00 24 Feb - 29 Mar
20 Apr - 26 Apr
4 May - 31 May
Presentation A
Activity Day Time Location Weeks
01 Monday 10:00 - 11:00 Elec 210 Electronics Lab 17 Feb - 23 Feb
Tutorial A
Activity Day Time Location Weeks
01 Tuesday 15:00 - 16:00 17 Feb - 29 Mar
20 Apr - 31 May

Examination and Formal Tests

Test A
Activity Day Time Location Weeks
01 Thursday 19:00 - 20:00 27 Apr - 3 May

Course Coordinator

Ciaran Moore


Assessment Due Date Percentage 
Test 25%
Project Inspection 10%
Homework 15%
Project Code 7%
Project Report 8%
Final Exam 35%

Indicative Fees

Domestic fee $975.00

International fee $5,500.00

* Fees include New Zealand GST and do not include any programme level discount or additional course related expenses.

For further information see Electrical and Computer Engineering.

All ENEL373 Occurrences

  • ENEL373-20S1 (C) Semester One 2020